Lec 01 Overview of the Course (Arif Butt @ PUCIT)

 

This is the introduction of the course “Computer Organization and Assembly Language Programming”. This video gives course information like a discussion about the course matrix and the links from where the e-books, tools, code snippets, and lecture slides, and other misc resources can be downloaded. This course will be having two parts in the first half of the course we will be designing and writing the HDL of a full-blown computer, will design its machine and assembly language, will write programs and execute those programs on the designed h/w architecture. At the end of the first half of the course, we will also design and write an Assembler (in C) for the designed computer. The second half of the course will deal with the assembly of the all-time famous x86-64 architecture.

Email: arif@pucit.edu.pk

Web:  http://www.arifbutt.me/ 

Sample Codes/Resources: https://bitbucket.org/arifpucit/coal-repo/src/  

Lec 02 HDL for Combinational Circuits – I (Arif Butt @ PUCIT)

 

Review of Boolean logic and some elementary logic gates. Types HDLs, e.g., System Verilog, Verilog, VHDL, and HDL by Noam+Shemon. Write HDL programs for AND, OR, and NOT gate chips using the universal built-in NAND gate. Where to download the hardware simulator for this course? A demo/description of the GUI and working of Hardware Simulator and interactive testing of the chips designed in this session.

Email: arif@pucit.edu.pk

Web: http://www.arifbutt.me/

Sample Codes/Resources: https://bitbucket.org/arifpucit/coal-repo/src/

Lec 03 HDL for Combinational Circuits – II (Arif Butt @ PUCIT)


Design and HDL code for XOR chip, using And, OR, Not gate chips. A demo of Verification of XOR chip using interactive chip testing in the h/w simulator. A brief overview of script-based chip testing. Writing script for testing of the designed XOR chip. A discussion on key players involved in a hardware construction project.

Email: arif@pucit.edu.pk

Web: http://www.arifbutt.me/

Sample Codes/Resources: https://bitbucket.org/arifpucit/coal-repo/src/

Lec 04 HDL for Combinational Circuits – III (Arif Butt @ PUCIT)


Design and HDL code for some standard combinational circuits like Encoder, Decoders, Multiplexers, and De-Multiplexer chips. A demo of Verification / Testing of these standard combinational chips using interactive chip testing in the h/w simulator.

Email: arif@pucit.edu.pk

Web: http://www.arifbutt.me/

Sample Codes/Resources: https://bitbucket.org/arifpucit/coal-repo/src/

Lec 05 HDL for Combinational Circuits – IV (Arif Butt @ PUCIT)


Design and HDL code for multi-bit gates. The concept of buses and the design of chips having buses as input. Design and code of And16, Or16, Not16, and Mux16 chips having 16-bits inputs. Design and code of And4way16 and similar chips having four inputs with each input of 16 bits.

Email: arif@pucit.edu.pk

Web: http://www.arifbutt.me/

Sample Codes/Resources: https://bitbucket.org/arifpucit/coal-repo/src/

Lec 06 Data Storage – I (Arif Butt @ PUCIT)

 

Data Representation in Computers, Unsigned, and Signed Numbers, Sign magnitude representation & its limitations, 1s Complement representation & its limitations, 2s Complement representation, Comparisons and pros and cons of each, Ranges and different Storage Sizes, Overflow in Unsigned & Signed Numbers, How the Hardware Detect an Overflow, Concept of Sign Extension, Encoding Characters and Strings (ASCII & Unicode)

Email: arif@pucit.edu.pk

Web: http://www.arifbutt.me/

Sample Codes/Resources: https://bitbucket.org/arifpucit/coal-repo/src/

Lec 07 Data Storage – II (Arif Butt @ PUCIT)

 

Encoding Real Number, Fixed Point Representation, Floating-Point Representations (IEEE-754), Storage layout, Conversion Examples, Range and Precision of IEEE-754, Arithmetic Operations, Overflow and Underflow, IEEE-754 Special Values

Email: arif@pucit.edu.pk

Web: http://www.arifbutt.me/

Sample Codes/Resources: https://bitbucket.org/arifpucit/coal-repo/src/

Lec 08 Design of ALU – I (Arif Butt @ PUCIT)

 

Review of HDL for Combinational Circuits, Designing a single bit Logic Unit
Writing HDL for Combinational Arithmetic Circuits like Half Adder, Full Adder, Full Subtractor, 16-bit Binary Adder (Add16 chip), 16-bit Incrementer (Inc16 chip), Demo of above chips on H/W Simulator

Email: arif@pucit.edu.pk

Web: http://www.arifbutt.me/

Sample Codes/Resources: https://bitbucket.org/arifpucit/coal-repo/src/