CPU Performance Equation, Single Cycle vs Multi Cycle CPU Architecture, Pipelined CPU Architecture, Pipeline Stages, Even vs Uneven pipelined stages, Pipelined Hazards, Solutions of Pipeline Hazards, CISC vs RISC Architecture
Email: arif@pucit.edu.pk
Sample Codes/Resources: https://bitbucket.org/arifpucit/coal-repo/src/